1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
In the conventional art, trench gates form a lattice pattern (see, for example, Japanese Patent Application Publication No. 2012-190938) in order to increase carrier injection enhanced effects (hereinafter, simply referred to as “the IE effects”) for a drift layer. Furthermore, in the conventional art, a first gate interconnection and a second gate interconnection, which are formed as stripes, are arranged parallel to each other and supplied with independent control signals from each other (see, for example, Japanese Patent Application Publication No. 2000-101076). Furthermore, in the conventional art, a first element unit and a second element unit in a semiconductor device are controlled by different signals (see, for example, Japanese Patent Application Publication No. 2012-238715).
Generally speaking, a trench is formed by defining a trench formation region at the front surface of a semiconductor substrate using a mask made of silicon oxide or the like and subjecting the trench formation region to etching. In a case where the trench formation region has a lattice pattern, a vertex is defined between every two sides. Here, the regions corresponding to the vertices are etched away more deeply than the regions corresponding to the sides. Thus, the trenches are deeper at the vertices than at the sides. Such variations in the depths of trenches may disadvantageously result in variations in the gate threshold voltages (Vth).